The present invention relates to a method of providing a vertical interconnect between a first and a second thin-film microelectronic device, wherein a vertical interconnect area is provided which is an area of overlap of a stack comprising a first electrically conducting area, an organic electrically insulating area and a second electrically conducting area, said first electrically conducting area being electrically connected to a terminal of said first microelectronic device and said second electrically conducting area being electrically connected to a terminal of said second microelectronic device.
Such a method is known from WO 99/10929, which discloses mechanically forming a vertical interconnect between a first and a second thin-film microelectronic device using a tool tip to make a notch in a vertical interconnect area of two organic electrically conducting areas which are separated from each other by an organic electrically insulating area. The tool tip is preferably tapered and has a preferred tip radius between 0.1 xcexcm and 5.0 xcexcm. The first and second electrically conducting areas are made of organic material including heavily doped semiconducting polymers, such as a polyaniline. The organic electrically insulating materials used for the insulating area are exemplified by a polyvinylalcohol or a polyvinylphenol.
Electronic circuits based partly or entirely on organic polymeric materials are foreseen to play a major role in the coming years in areas of electronics where low cost or flexibility is an essential requirement. Application areas such as electronic barcodes and smart cards are the current target areas since the prime concern for such products is cost. Organic polymeric materials are easy to apply by known techniques such as spin coating or printing and thus offer significant potential cost savings over conventional silicon technology where photolithography, implantation and etching are necessary. In addition polymeric materials offer excellent mechanical properties such as flexibility.
In integrated circuits (ICs) which are constituted by a plurality of thin-film microelectronic devices, for example a plurality of field-effect transistors, memory units, rectifiers, diodes as well as antennas interconnects between such devices are to be provided. An interconnect provides an electrical connection between a terminal of a first and a second thin-film microelectronic device. Sometimes, it is necessary to provide an interconnect which extends through a stack of layers. An interconnect of this type is referred to as a vertical interconnect or, in short, a xe2x80x9cviaxe2x80x9d.
In silicon-based IC technology, vertical interconnects are made by photo-lithographically defining a contact window, etching so as to obtain a contact hole and, subsequently, filling the contact hole by depositing metal; see, e.g., VLSI Technology, ed. Sze, McGraw-Hill (1983), p 447.
Microelectronic devices consisting substantially of organic materials have been disclosed, for example by Garnier et al., Science (1994) 265:1684-1686, but no methods of making vertical interconnects between thin film devices were mentioned. Microelectronics based on organic materials may be effectively used in applications where the use of silicon-based technology is prohibitively expensive.
U.S. Pat. No. 4,702,792 describes a method of forming fine conductive lines, patterns and connectors, wherein polymeric photoresist material is applied to a substrate and is patterned to form openings and spaces which are then filled with conductive material of metal or metal alloy. The patterned photoresist is preferably treated with an organometallic compound to create an etch-resistant form of the photoresist. Excess conductive material is removed by chemical-mechanical polishing to expose the polymeric material. No disclosure is made of a vertical interconnect between a first and second thin-film microelectronic device, such as an integrated circuit.
U.S. Pat. No. 5,567,550, U.S. Pat. No. 5,677,041 and U.S. Pat. No. 5,691,089 describe the fabrication of a mask for making integrated circuits formed in radiation sensitive material, in which a doped radiation sensitive layer, preferably of polyimide, is formed on a substrate, un undoped polyimide layer is formed over the doped polyimide layer which is radiated to form first and second source drain regions extending to a top portion of the doped polyimide region. A top portion of the undoped polyimide is also irradiated to form a gate region between the first source/drain region and the second source/drain region. A channel is thereby formed in the doped layer beneath the gate region.
U.S. Pat. No. 5,689,428 discloses integrated circuits, transistors, data processing systems etc. which are made by a process including steps of applying an electrical resistance body of radiatively dosed radiation sensitive polymeric material. The radiation sensitive material preferably comprises a polyimide.
EP-A-0 399 299 discloses electron discharge layers containing electrically conductive polymeric materials comprising doping precursors which generate dopants upon exposure of energy. Conductivity can be selectively induced in the polymer by selectively doping under selective exposure to a source of energy which causes the reagent to decompose to dope those regions in the polymer which are exposed to the energy forming a conductive polymer in exposed regions. In the exposed region/the polymer is rendered insoluble and in the unexposed regions the polymer is soluble and can thereby be removed to act as a negative photoresist which is selectively electrically conducting.
In polymeric integrated circuits, mechanical techniques are currently used for providing vertical interconnects between thin-film electronic devices; see WO 99/10929, mentioned above. A drawback of mechanical vertical interconnects is the limited throughput due to the sequential nature of the process and the limited positional accuracy which requires the use of a relatively large surface area. Moreover, a mixture of technologies such as photolithography and mechanical stitching is not desirable for the realization of a reel-to-reel process.
Therefore, an object of the present invention is to provide an efficient method for producing vertical interconnects which preferably are substantially made of organic polymeric materials, which obviates the problems mentioned.
It has now been found that vertical interconnects in substantially plastic electronics can be efficiently and reliably produced photochemically, wherein a photochemical resist is used which is chosen such that the part outside the overlapping area is maintained as electrically insulating area or part thereof, resulting in products with excellent properties. The method is therefore suitable for large scale production.
In accordance with the present invention there is provided a method of producing a vertical interconnect between a first and a second thin-film microelectronic device, wherein a vertical interconnect area is provided which is an area of overlap of a stack of layers comprising a first electrically conducting area, an organic electrically insulating area, a second organic electrically conducting area, and optionally an organic electrically semiconducting area, said areas being formed one by one, and at least one of said first or said second electrically conducting areas being positioned adjacent to and after said organic electrically insulating area, said first electrically conducting area being electrically connected to a terminal of said first microelectronic device and said second electrically conducting area being electrically connected to a terminal of said second microelectronic device, characterized in that
said organic electrically insulating area comprises photoresist material,
said insulating area is removed within said area of overlap before said adjacent first or said second electrically conducting area is positioned, and
said removed insulating area is substituted by an electrically conducting area which is extended from at least said first or said second electrical conducting area, thereby forming the vertical interconnect.
In a preferred embodiment of the invention, the layer forming said organic electrically insulating area comprising photoresist material is removed photochemically within the area of overlap. Such a method comprises, for example, mixing the organic insulating area with a photoinitiator and/or a crosslinking agent, selectively exposing said mixture e.g. through a mask within the overlapping area to an energy source, for example deep UV radiation, such that the selective crosslinking of the insulator is catalyzed by the photoinitiator. The non-exposed parts are then removed in a conventional manner, for example by washing with propyleneglycol methyl ether acetate, or any other suitable agent known in the art.
Alternatively, the solubility of the exposed parts is improved by exposing the mixture to deep UV radiation, or another conventional energy source, and these exposed parts are then removed. Therefore, in general, the solubility of the unexposed area is different from that of the exposed area, enabling the removal of materials which have been made soluble from said insulating area.
In a particularly preferred embodiment of the invention the organic electrically insulating area consists essentially of adapted photosensitive material, which preferably serves as a gate dielectric.
Examples of photoresists (e.g. adapted photosensitive material) which can be suitably used in the practice of the present invention include hard-baked novolaks, conventional photoresists comprising polymers such as polyvinylphenols (e.g. UV flood-exposed PVPs), polyglutarimides, polyimides, polyvinylalcohols, polyisoprenes, polyepoxy-based resins, polyacrylates, polyvinylpyrrolidone, p-hydroxystyrene polymers, and melamino polymers. Therefore, the process according to the present invention is generally applicable in a wide range of applications. When a hard-baked novolak is used, the novolak photoresist is typically exposed to a source of radiation to which it is sensitive, in order to create a latent image. This latent image is subsequently developed using standard aqueous base developer. After development, the patterned resist is baked at a temperature of at least 150xc2x0 C., to provide the hard-baked patterned novolak resist. Commercially available novolak photoresists of the type that can be suitably used in the practice of the present invention include HPR 504. It will be evident to one skilled in the art that it may be desirable to select a photoresist which can be treated by a xe2x80x9cneutralxe2x80x9d developer based on organic solvents, such as toluene or xylene propylene glycol methylether acetate, in order to avoid possible affects to adjacent layers. For example, when acid-doped conductive polymers are applied, such as polyanilines, the use of basic developers is not favored since this may lead to removal of the doped materials and, accordingly, to a higher sheet-and contactresistance. xe2x80x9cStack integrityxe2x80x9d is therefore crucial. Particularly preferred groups of photoresists are selected from the group of polyisoprenes and polyepoxy-based resins, and a commercially available polyepoxy-based photoresist which can be suitably used is SU8. The SU8 is a negative, epoxy-type, near-UV photoresist.
In another preferred embodiment of the invention, said organic electrically insulating area comprises an organic electrically insulating polymeric compound which is capable of being crosslinked, usually with a crosslinking agent. There are no restrictions on the selection of polymeric insulators except that they are most preferably photochemically patterned. It has been found that polyvinylphenol and polyvinylalcohol are suitable insulating polymeric materials, of which polyvinylphenol is preferred. Suitable crosslinking agents include aminoplasts, such as hexamethoxymethylmelamine (HMMM).
In still another preferred embodiment of the invention, said organic electrically insulating area further comprises a photoinitiating agent which upon exposure to photoenergy, preferably UV radiation, catalyses the crosslinking of said organic electrically insulating polymeric compound and said crosslinking agent. A variety of compounds which are known in the art can be used as photoinitiators, such as onium salts, triflate salts and bisazides. A suitable and preferred photoinitiator is, for example, biphenyliodoniumhexa-fluoroborate.
Although the present inventors do not wish to be bound to any theory as to how and why the method works, the method is found to be simple, accurate, and very reliable. Typically, it is possible to make 118 vias, each via having a contact resistance in the range of from about 10 kxcexa9 up to about 1 Mxcexa9 on average (when the electrically semiconducting area is positioned between the said two electrically conducting areas, the conventional xe2x80x9ctop gate structurexe2x80x9d), in a single run without a single failure. The method appears therefore to be effective, substantially irrespective of the material properties of the organic materials used. The contact resistance in these structures is dominated by the Ohmic conductivity of the semiconducting PTV film and is low enough to be applied in electronic devices such as polymeric integrated circuits.
Alternatively, the semiconducting area is positioned on top of a stack comprising the first electrically conducting area having a gate electrode, the insulating area and the second electrically conducting area having a source and a drain electrode. The via in this stack, also referred to as a xe2x80x9cbottom gate structurexe2x80x9d, has typically a contact resistance in the range of 100 xcexa9 to 2 kxcexa9. Hundreds of such vias can be manufactured without any problem in a single run without a single failure.
The choice of the electrically conducting material used to form the first and second electrically conducting areas is not critical either. Preferably, the areas consist of an organic substance. Suitable examples include heavily doped semiconducting polymers known per se, such as a polyaniline (PANI), a polythiophene, a polypyrrole, a polyphenylene, and a polyphenylenevinylene.
Alternatively, heavily doped substituted derivatives of these polymers can be applied. Examples of suitable substituents include alkyl and alkoxy groups and ring-shaped groups, such as alkylenedioxy. Preferably, the substituent groups have a carbon chain of 1 to about 10 carbon atoms. A preferred example is poly-3,4-ethylenedioxythiophene (PEDOT).
in another preferred embodiment of the method according to the invention, the first and/or second electrically conducting area comprises an electrically conducting polyaniline. By using electrically conducting polyaniline, the conductivity of which typically is 10 to 100 S/cm, a vertical interconnect can be made having a contact resistance as low as 1 kxcexa9. For many applications, this resistance is sufficiently small. For example, if the via interconnects field-effect transistors consisting substantially of organic materials, the current flowing through the via will typically be in the order of 10xe2x88x929 to 10xe2x88x926 amps. Given a resistance of 3 kxcexa9, the resulting voltage drop across the vertical interconnect is negligible.
Generally, the first and second electrically conducting areas are patterned using a conventional, preferably photochemical patterning technique. For example, when a doped polyaniline film is applied as the electrically conducting area is typically prepared by dissolving polyaniline doped P+ with camphorsulphonic acid in a solvent such as m-cresol, adding a photoinitiator to this solution which is then spin-coated onto a substrate such as polyimide foil. The film is exposed in a nitrogen atmosphere through a mask to deep UV radiation. Upon exposure the conducting aniline is reduced to the nonconducting form. As a result, conducting tracks are embedded in an otherwise insulating film. The height differences between the exposed and unexposed parts of the film, with a thickness of typically 0.2 xcexcm, is less than 50 nm and therefore no further planarization is necessary. If desired, the exposed part, i.e. the nonconducting form, is removed by using a conventional technique, such as a suitable solvent like N-methyl pyrrolidone. In certain embodiments of the invention, it is preferred to remove the nonconducting form before applying a next layer. For example, when fabricating a bottom gate structure (see below), it is generally recommended to remove said nonconducting form from the patterned second electrically conducting area before the organic semiconducting layer is applied on top.
It may be useful to apply a metal layer as the first electrically conducting area together with or instead of the organic electrically conducting layer. The metal layer may be comprised of any. conventional metal or alloy or mixture of metals which are known in the art for this purpose, for example copper or copper-based alloys. Preferably, the metal layer is essentially made of a thin gold or a gold-containing alloy or mixture (e.g. gold-titanium) which is not affected by chemicals used in the manufacturing of adjacent layers. The metal layer is usually deposited by evaporation on the substrate, using conventional techniques and is then patterned also using conventional techniques, such as etching with KI/I2.
The stack optionally comprises an organic electrically semiconducting area which may be situated between any of the areas described above depending on its intended use, for example between the first electrically conducting area and the insulating area or between the insulating area and the second electrically conducting area, or the organic semiconducting area may be the upper layer (e.g. in a bottom-gate configuration). The choice of the organic semiconducting material is not very critical and inter alia depends on the intended use. In principle any conjugated polymer and oligomeric analogue with semiconducting properties which is suitable for making field-effect transistors can be used. Examples of such suitable materials include polyacenes, polypyrroles, polyphenylenes, polythiophenes, polyphenylene-vinylenes, poly(di)acetylenes, polyfuranylenes-vinylenes, polyfuranes, and polyanilines. Alternatively, substituted derivatives of these polymers are applied. Examples of suitable substituents include alkyl and alkoxy groups and ring-shaped groups, such as alkylenedioxy. Preferably, the substituent groups have a carbon chain of 1 to 10 carbon atoms. A suitable and preferred semiconducting material comprises poly(thienylene vinylene) or a poly-3-alkylthiophene, such as poly-3-hexylthiophene.
The stack of electrically conducting, semiconducting and insulating areas is preferably carried by a supporting substrate. Such a supporting substrate suitably comprises a synthetic polymeric resin, such as a polyimide. Glass or silica supporting substrates are also suitable.
The vertical interconnect area has a surface area, as defined by the size of one of the electrically conducting areas. This surface area is in the order of 10 xcexcmxc3x9710 xcexcm to 50 xcexcmxc3x9750 xcexcm. Further on, the vertical interconnect area has a cross-sectional size. This size, as defined by the smallest conducting area in the via stack, is suitably about 2 xcexcmxc3x972 xcexcm to 10 xcexcmxc3x9710 xcexcm.
A suitable thickness of the stack constituting the vertical interconnect area is 2 xcexcm or less. A larger thickness, for example from 5 xcexcm to 20 xcexcm, is also possible.
Preferably, the stack has a thickness in the order of 700 nm to 1 xcexcm. This allows for ultrathin electronic devices, which can be integrated into packages, security documents, banknotes and the like.
By simply expanding the stack comprising the vertical interconnect area with further electrically conducting areas and/or further insulating areas, the method of the present invention can be used to provide multilevel vertical interconnects.
The method according to the invention is to provide a vertical interconnect between a first and a second thin-film microelectronic device. Obviously, this can only be done if the first and second electrically conducting areas of the vertical interconnect area are connected to the first and second thin-film microelectronic device, respectively. Although the method can be suitably used in conjunction with any type of organic thin-film microelectronic device, the method is particularly effective in forming a vertical interconnect between field-effect transistors consisting substantially of organic materials.
In a further aspect, the present invention relates to a structure comprising a vertical interconnect between a first and a second thin-film microelectronic device wherein a vertical interconnect area is provided which is an area of overlap of a stack of layers comprising:
a first electrically conducting area, which is electrically connected to a terminal of said first microelectronic device
an organic electrically insulating area separating said first and said second thin-film microelectronic device outside said area of overlap, said organic electrically insulating area comprising adapted photoresist material,
a second organic electrically conducting area, which is electrically connected to a terminal of said second microelectronic device,
optionally an organic electrical semiconducting area, which is positioned between said first electrically conducting area and said organic electrical insulator or between said organic electrically insulator and said second electrically conducting area, or which is an outside layer opposite to the support, wherein at least one of said first or said second electrically conducting areas is positioned adjacent to said organic electrically insulating area, said vertical interconnect being an organic electrically conductive area which extends from at least one of said first or said second electrically conducting area.
In a particular preferred embodiment of the invention the electrically semi-conducting area is positioned at the outside of the stack, preferably opposite the substrate (the so-called xe2x80x9cbottom gatexe2x80x9d structure or geometry). Typically, vertical interconnects in such bottom gate structure each have a contact resistance which is usually less than 1 kxcexa9 on average. If desired, the stack is provided with a protective coating. The bottom-gate geometry offers a number of advantages including the following. Firstly, it is not restricted to insoluble, noncrystalline materials as the active semiconductor. This is illustrated in the present invention by FETs made from pentacene, a highly crystalline organic molecule. Secondly, it is preferable that the organic semiconductor layer is processed in the final step since the performance of the semiconductor, and hence the performance of a transistor, can be adversely affected by exposure to chemicals and/or heating steps in any further processing steps. Thirdly, vertical interconnects with low contact resistance are readily obtainable by photolithographically patterning the dielectric insulator layer, whereas in a top-gate transistor the contact resistance of the vertical interconnects is increased due to the high-ohmic semiconductor that is positioned between the source-drain electrode layer and the gate electrode layer. A semifabricate comprising the stack conductor-insulator-conductor usually is very stable.
The present invention further relates to electronic devices comprising at least one vertical interconnect which is obtainable by the method according to this invention, or a structure comprising an vertical interconnect, as defined above. Electronic devices include ICs displays, smartcards, identification tags and the like.
A preferred electronic device includes an integrated circuit, which preferably substantially consists of organic materials. As a result of the low cost of organic materials and their ease of processing, an integrated circuit consisting substantially of organic materials, in short an organic IC, can be manufactured at a much lower cost than a siliconbased IC.
In a particularly preferred embodiment, the thin-film devices are part of the stack of layers used to form the vertical interconnect area. In this case, a stack comprising only four layers, usually three of which are patterned, is sufficient to provide an IC. A thin-film microelectronic device which may be conveniently accommodated by such a four-layered stack is a field-effect transistor.
Examples of circuits which can be successfully implemented in this manner include logic gates, such as an invertor, a NAND gate, a NOR gate, and an AND gate as well as combinations thereof, such as flip flops, frequency dividers and ring oscillators. In addition, the process according to the invention can also be used for the production of Mask-ROMs. Examples of such applications of vertical interconnects are given in our WO 99/10929, which is incorporated herein by reference.
The invention relates to an electronic device further comprising a second electrically conducting area which is substantially of metal instead of organic material as is claimed in claim 18.
In a preferred embodiment the electronic device is a circuit comprising a first and a second thin-film microelectronic device substantially consisting of organic materials as is claimed in claim 19.
These and other aspects of the invention will be apparent from and elucidated with reference to the more specific embodiments described hereinafter.
In the drawings,
FIGS. 1 and 2 are schematic cross-sectional views of a vertical interconnect area in a laminate comprising a substrate, a first conductive area, a semiconducting area, an insulating area, and a second conductive area, as described in Example 1,
FIG. 3 is a schematic cross-sectional view of a vertical interconnect area in a laminate comprising a substrate, a first conductive area, an insulating area, and a second conductive area, as described in Example 5, and
FIG. 4 is a schematic cross-sectional view of a vertical interconnect in a bottom gate structure, as described in Examples 7-10.